Past decisions need to be accurately sampled in application of a decision feedback equalizer (DFE). A non-consecutive sampling clock occurs from forwarded source-synchronous clock implementation of fourth generation double data rate (DDR4) memory specification. The forwarded source-synchronous clock will be restarted following a targeted access command. With conventional techniques, a maximum DFE margin will not be equalized due to error propagation of stale or incorrect past history at the first data transition bit, causing a margin reduction.
It would be desirable to implement a method and/or apparatus to nullify incorrect sampled data contribution in a decision feedback equalizer (DFE) at restart of forwarded clock in a memory system.